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ds07-12514-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89670/a series mb89673/677a/p677a/pv670a n description the mb89670/a series has been developed as a line of proprietary 8-bit, single-chip microcontrollers. in addition to the f 2 mc*-8l cpu core which can operate at low voltage but at high speed, the microcontrollers contain pheripheral functions such as timers, a serial interface, an a/d converter, a uart, an up/down counter, and an external interrupt. the mb89670/a series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features ?f 2 mc-8l family cpu core instruction set optimized for controllers ? high-speed processing at low voltage ? minimum execution time: 0.4 m s/3.5 v, 0.8 m s/2.7 v, 2.0 m s/2.2 v ? i/o ports: max. 69 channels (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. (fpt-80p-m11) (fpt-80p-m06) (mqp-80c-p01) 80-pin plastic qfp 80-pin plastic qfp 80-pin ceramic mqfp
2 mb89670/a series (continued) ? timers: 9 channels (mb89670a: 12 channels) 8-bit pwm timer: 3 channels (mb89670a: 6 channels) (also usable as a reload timer) 16-bit timer/counter 21-bit time-base timer 8/16-bit timer (8 bits 2 channels or 16 bits) 8/16-bit up/down counter timer (8 bits 2 channels or 16 bits) ? two serial interfaces 8-bit synchronized serial: 1 channel (switchable transfer direction allows communication with various equipment.) uart: 1 channel (with full-duplex double buffer) ? external interrupts: 8 channels eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? buzzer output ? 10-bit a/d converter 8-channel input ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) ? bus interface function including hold and ready functions
3 mb89670/a series n product lineup (continued) mb89677a mb89p677a mb89pv670a classification mass production products (mask rom products) one-time prom product (for development) piggyback/ evaluation product (for development) rom size 8 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) 32 k 8 bits (internal prom) 48 k 8 bits (external rom) ram size 384 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s/10 mhz to 6.4 m s/10 mhz interrupt processing time: 3.6 m s/10 mhz to 57.6 m s/10 mhz ports output ports (n-channel open-drain): 14 (12 also serve as peripherals.) output ports (cmos): 8 (all also serve as peripherals.) i/o ports (n-channels open-drain): 7 (all also serve as peripherals.) i/o ports (cmos): 32 (all also serve as peripherals.) input ports: 8 (all also serve as peripherals.) to t a l : 6 9 option specify when ordering masking set with eprom programmer setting not possible 21-bit time- base timer 21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms/10 mhz) 8/16-bit up/ down counter 8 bits 2 channels or 16 bits 1 channel timer operation up/down counter operation phase difference counting (successive double mode, quadruple mode) 16-bit timer/ counter 16-bit timer operation 16-bit event counter operation (edge selectability) 8/16-bit timer counter 8 bits 2 channels or 16 bits 1 channel reload timer operation (toggled output capable) event counter operation 8-bit pwm timer 1, 8-bit pwm timer 2 8 bits 2 channels reload timer operation (toggled output capable) 8 bits 2 channels pwm operation (four fixed frequency) 8 bits 1 channel ppg operation (variable frequency) capable of output switching between 2 channels 8-bit pwm timer 3, 8-bit pwm timer 4, 5, 6 8-bit reload timer operation (toggled output capable) 8-bit pwm operation (four fixed frequency) capable of output switching between 2 channels 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) mb89673 *1 part number parameter
4 mb89670/a series (continued) *1: 8-bit pwm timer 4, 5, and 6 is not provided for the mb89673. *2: the minimum operating voltage varies with the operating frequency, the function, and the connected ice. n package and corresponding products : available : not available * : lead pitch converter sockets (manufacturer: sun hayato co., ltd.) are available 80qf-80qf2-8l-up + (mqp-80c-p01 or fpt-80p-m06) ? for conversion to fpt-80p-m11 80qf-80qf2-8l-dwn note: for more information about each package, see section n package dimensions. mb89677a mb89p677a mb89pv670a uart variable data length (7 or 8 bits) internal baud rate generator error detection function intenal full-duplex double buffer nrz transfer format clk synchrnous/asynchronous data transfer capable 10-bit a/d converter 10 bit 8 channels external interrupt 8 channels (rising edge/falling edge) operating voltage *2 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mbm27c512-20tv (lcc package) package mb89673 mb89677a mb89p677a mb89pv670a fpt-80p-m06 fpt-80p-m11 * mqp-80c-p01 mb89673 *1 part number parameter
5 mb89670/a series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the mb89p677a, the program area starts from address 8007 h but on the mb89677a and mb89pv670a starts from 8000 h . (on the mb89p677a, addresses 8000 h to 8006 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89677a and mb89pv670a, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the mb89p677a.) ? the stack area, etc., is set at the upper limit of the ram. ? the external area is used. 2. current consumption ? in the case of the mb89pv670a, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following point: ? options are fixed on the mb89pv670a. n correspondence between the mb89670/a and mb89670r/ar series ? the mb89670r/ar series is the reduction version of the mb89670/a series. for their differences, refer to the mb89670r/ar series data sheet. mb89670/a series mb89673 mb89677a mb89p677a mb89pv670a mb89670r/ar series mb89673r mb89675r mb89677ar
6 mb89670/a series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p73/ui p72/uo p71/uck p70/bz1 p83 p82 p81 p80 mod0 mod1 x0 x1 v ss rst p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p66/int6 p67/int7 p84 p85 v ss p40/pwm00 p41/pwm01 v cc p42/pwm10/bz2 p43/pwm11 p44/tci p45/tco1 p46/tco2 p47/ec p30/pwm20 p31/pwm21 p32/udz1 p33/udb1 p34/uda1 p35/udz2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p74/sck p75/so p76/si av ss avr av cc p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p60/int0/adst p61/int1 p62/int2 p63/int3 p64/int4 p65/int5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p21/hak p20/bufc p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 p37/uda2 p36/udb2 (fpt-80p-m11) (top view)
7 mb89670/a series ? pin assignment on package top (mb89pv670a only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 81 n.c. 89 a2 97 n.c. 105 oe /v pp 82a1590a198o4106n.c. 83a1291a099o5107a11 84 a7 92 n.c. 100 o6 108 a9 85 a6 93 o1 101 o7 109 a8 86 a5 94 o2 102 o8 110 a13 87 a4 95 o3 103 ce 111 a14 88 a3 96 v ss 104 a10 112 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p75/so p74/sck p73/ui p72/uo p71/uck p70/bz1 p83 p82 p81 p80 mod0 mod1 x0 x1 v ss rst p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p64/int4 p65/int5 p66/int6 p67/int7 p84 p85 v ss p40/pwm00 p41/pwm01 v cc p42/pwm10/bz2 p43/pwm11 p44/tci p45/tco1 p46/tco2 p47/ec p30/pwm20 p31/pwm21 p32/udz1 p33/udb1 p34/uda1 p35/udz2 p36/udb2 p37/uda2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p76/si av ss avr av cc p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p60/int0/adst p61/int1 p62/int2 p63/int3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 100 99 98 97 96 95 94 110 111 112 81 82 83 84 (top view) (fpt-80p-m06) (mqp-80c-p01) each pin inside the dashed line is for the mb89pv670a only.
8 mb89670/a series n pin description (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function qfp *1 qfp *2 mqfp *3 11 13 x0 a clock oscillator pins 12 14 x1 9 11 mod0 b operating mode selection pins connect directly to v cc or v ss . 10 12 mod1 14 16 rst c reset i/o pin this pin is an n-ch open-drain output type with pull-up resistor and a hysteresis input. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 38 to 31 40 to 33 p00/ad0 to p07/ad7 d general-purpose i/o ports when an external bus is used, these ports function as multiplex pins of lower address output and data i/o. 30 to 23 32 to 25 p10/a08 to p17/a15 general-purpose i/o ports when an external bus is used, these ports function as upper address output pins. 22 24 p20/bufc f general-purpose output port when an external bus is used, this port can also be used as a buffer control output by setting the bctr. 21 23 p21/hak f general-purpose output port when an external bus is used, this port can also be used as a hold acknowledge output by setting the bctr. 20 22 p22/hrq d general-purpose output port when an external bus is used, this port can also be used as a hold request input by setting the bctr. 19 21 p23/rdy d general-purpose output port when an external bus is used, this port functions as a ready input. 18 20 p24/clk f general-purpose output port when an external bus is used, this port functions as a clock output. 17 19 p25/wr f general-purpose output port when an external bus is used, this port functions as a write signal output. 16 18 p26/rd f general-purpose output port when an external bus is used, this port functions as a read signal output. 15 17 p27/ale f general-purpose output port when an external bus is used, this port functions as an address latch signal output.
9 mb89670/a series (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function qfp *1 qfp *2 mqfp *3 46 48 p30/pwm20 d general-purpose i/o port also serves as the pwm20 output for the 8-bit pwm timer. 45 47 p31/pwm21 d general-purpose i/o port also serves as the pwm21 output for the 8-bit pwm timer. 44 46 p32/udz1 e general-purpose i/o port also serves as the z-phase input for the 16-bit up/down counter/timer. 43 45 p33/udb1 e general-purpose i/o port also serves as the b-phase input for the 16-bit timer/ counter. 42 44 p34/uda1 e general-purpose i/o ports also serves as the a-phase input for the 16-bit up/down counter/timer. 41 43 p35/udz2 e general-purpose i/o port also serves as the z-phase input for the 16-bit up/down counter/timer. 40 42 p36/udb2 e general-purpose i/o port also serves as the b-phase input for the 16-bit up/down counter/timer. 39 41 p37/uda2 e general-purpose i/o port also serves as the a-phase input for the 16-bit up/down counter/timer. 55 57 p40/pwm00 d general-purpose i/o port also serves as the pwm00 output for the 8-bit pwm timer. 54 56 p41/pwm01 d general-purpose i/o port also serves as the pwm01 output for the 8-bit pwm timer. 52 54 p42/pwm10/ bz2 d general-purpose i/o port also serves as the pwm10 and the bz2 output for the 8- bit pwm timer. 51 53 p43/pwm11 d general-purpose i/o port also serves as the pwm11 output for the 8-bit pwm timer. 50 52 p44/tci e general-purpose i/o port also serves as the tci input for the 8/16-bit timer/ counter. 49 51 p45/tco1 d general-purpose i/o port also serves as the tco1 output for the 8/16-bit timer/ counter.
10 mb89670/a series (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function qfp *1 qfp *2 mqfp *3 48 50 p46/tco2 d general-purpose i/o port also serves as the tco2 output for the 8/16-bit timer/ counter. 47 49 p47/ec e general-purpose i/o port also serves as input for the16-bit timer/counter. the ec input is a hysteresis input type. 74 to 67 76 to 69 p50/an0 to p57/an7 i n-ch open-drain output ports also serve as the analog input for the a/d converter. 66 68 p60/int0/ adst j general-purpose input port the software pull-up resistor is provided. also serves as an external interrupt input (int0) and an a/d converter external activation. this port is a hysteresis input type. 65 to 59 67 to 61 p61/int1 to p67/int7 j general-purpose input ports a software pull-up resistor is provided. also serve as an external interrupt input (int1 to int7). these ports are a hysteresis input type. 4 6 p70/bz1 g n-ch open-drain i/o port also serves as a buzzer output. 3 5 p71/uck k n-ch open-drain i/o port also serves as a uart clock i/o (uck) switchable to cmos. 2 4 p72/uo k n-ch open-drain i/o port also serves as a uart data output (uo) switchable to cmos. 1 3 p73/ui g n-ch open-drain i/o port also serves as a uart data input (ui). 80 2 p74/sck k n-ch open-drain i/o port also serves as the clock i/o for the serial i/o (sck) switchable to cmos. 79 1 p75/so k n-ch open-drain i/o port also serves as the data output (so) for the serial i/o switchable to cmos. 78 80 p76/si g n-ch open-drain i/o port also serves as the data input (si) for the serial i/o. 8 to 5 57, 58 10 to 7 59, 60 p80 to p83 p85, p84 h n-ch open-drain output ports 53 55 v cc power supply pin 13, 56 15, 58 v ss power supply (gnd) pin 75 77 av cc a/d converter power supply pin 76 78 avr a/d converter reference voltage input pin 77 79 av ss a/d converter power supply pin use this pin at the same voltage as v ss .
11 mb89670/a series ? external eprom pins (mb89pv670a only) pin no. pin name i/o function 82 83 84 85 86 87 88 89 90 91 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 93 94 95 o1 o2 o3 i data input pins 96 v ss o power supply (gnd) pin 98 99 100 101 102 o4 o5 o6 o7 o8 i data input pins 103 ce o rom chip enable pin outputs h during standby. 104 a10 o address output pin 105 oe /v pp o rom output enable pin outputs l at all times. 107 108 109 a11 a9 a8 o address output pins 110 a13 o 111 a14 o 112 v cc o 81 92 97 106 n.c. internally connected pins be sure to leave them open.
12 mb89670/a series n i/o circuit type (continued) type circuit remarks a crystal or ceramic oscillation type ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input d ? cmos output ? cmos inout ? pull-up resistor optional (except p22 and p23) e ? cmos output ? cmos input ? the peripheral is a hysteresis input type. ? pull-up resistor optional x1 x0 standby control signal r p-ch n-ch n-ch r p-ch p-ch p-ch n-ch r p-ch peripheral port
13 mb89670/a series (continued) type circuit remarks f ? cmos output g ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional h ? n-ch open-drain output i ? n-ch open-drain output ? analog input j ? hysteresis input ? with software pull-up resistor k ? cmos output ? hysteresis input ? pull-up resistor optional p-ch n-ch n-ch r p-ch p-ch n-ch n-ch analog input p-ch r p-ch pull-up control signal p-ch n-ch r p-ch
14 mb89670/a series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
15 mb89670/a series n programming to the eprom on the mb89p677a the mb89p677a is an otprom version of the mb89670/a series. 1. features ? 32-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in the eprom mode is diagrammed below. 0000 h 0007 h 7fff h program area (eprom) 8000 h 8007 h ffff h option area prom external area i/o register 0480 h 0000 h 0080 h 0100 h 0200 h normal operating mode eprom mode (corresponding addresses on the eprom programmer) ram option area
16 mb89670/a series 3. programming to the eprom in eprom mode, the mb89p677a functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h (note that addresses 8007 h to ffff h while operating as a normal operating mode assign to 0007 h to 7fff h in eprom mode). load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see 7. bit map for prom options.) (3) program with the eprom programmer. 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: depending on the eprom programmer, inserting a capacitor of about 0.1 m f between v pp and v ss or v cc and v ss can stabilize programming operations. package compatible socket adapter fpt-80p-m11 rom-80qf2-28dp-8l fpt-80p-m06 rom-80qf-28dp-8l2 program, verify aging +150 c, 48 hrs. data verification assembly
17 mb89670/a series 7. prom option bit map the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: notes: set each bit to 1 to erase. do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable vacancy readable vacancy readable vacancy readable reset pin output 1: yes 0: no power-on reset 1: yes 0: no oscillation stabilization time 00: 2 4 /f c 10: 2 17 /f c 01: 2 14 /f c 11: 2 18 /f c 0001 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0002 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0003 h p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 0004 h vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable 0005 h vacancy readable vacancy readable vacancy readable p74 pull-up 1: no 0: yes p73 pull-up 1: no 0: yes p72 pull-up 1: no 0: yes p71 pull-up 1: no 0: yes p70 pull-up 1: no 0: yes 0006 h vacancy readable vacancy readable vacancy readable vacancy readable p04 to p07 pull-up 1: no 0: yes p00 to p03 pull-up 1: no 0: yes p76 pull-up 1: no 0: yes p75 pull-up 1: no 0: yes
18 mb89670/a series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c512-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in each mode is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c512. (2) load program data into the eprom programmer at 4000 h to ffff h . (3) program to 4000 h to ffff h with the eprom programmer. package adapter socket part number lcc-32(rectangle) rom-32lc-28dp-yg 4000 h 8007 h ffff h not available eprom 48 kb ffff h ram prom 48 kb i/o normal operating mode corresponding address on the eprom programmer * * external area 0000 h 8000 h 4000 h 0480 h 0080 h 0000 h 8007 h 8000 h address *: note that for the mb89p677a this area comprise an option setting area.
19 mb89670/a series n block diagram 1. mb89673 ram cpu rom uart x0 x1 rst f 2 mc-8l 8 8 6 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc p80 to p85 p60/int0/adst to p67/int7 p50/an0 to p57/an7 avr 8 8 p37/uda2 p36/udb2 p35/udz2 p34/uda1 p33/udb1 p32/udz1 p47/ec p46/tco2 p45/tco1 p44/tci p43/pwm11 p42/pwm10/bz2 p41/pwm01 p40/pwm00 p31/pwm21 p30/pwm20 p73/ui p72/uo p71/uck p76/si p75/so p74/sck p70/bz1 av cc av ss oscillator clock controller reset circuit (wdt) cmos i/o port external bus interface cmos output port n-ch open-drain output port 10-bit a/d converter input port external interrupt internal bus time-base timer cmos i/o port 16-bit up/down counter 8-bit up/down counter 16-bit timer/counter 8/16-bit timer 8-bit timer 8-bit timer 2-channel 8-bit pwm timer 8-bit timer #2 8-bit timer #1 8-bit pwm timer #3 8-bit serial buzzer output n-ch open-drain i/o port 8-bit up/down counter
20 mb89670/a series 2. mb89677a/89p677a/89pv670a ram cpu rom x0 x1 rst f 2 mc-8l 8 8 6 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc p80 to p85 p60/int0/adst to p67/int7 p50/an0 to p57/an7 8 8 p37/uda2 p36/udb2 p35/udz2 p34/uda1 p33/udb1 p32/udz1 p47/ec p46/tco2 p45/tco1 p44/tci p40/pwm00 p42/pwm10/bz2 p76/si p75/so p74/sck p70/bz1 p30/pwm20 p31/pwm21 p41/pwm01 p43/pwm11 uart p73/ui p72/uo p71/uck avr av cc av ss oscillator clock controller reset circuit (wdt) cmos i/o port external bus interface cmos output port n-ch open-drain output port 10-bit ad converter input port external interrupt internal bus time-base timer cmos i/o port 16-bit up/down counter 8-bit up/down counter 16-bit timer/counter 8/16-bit timer 8-bit timer 8-bit timer 8-bit pwm timer #3 8-bit pwm timer #4 8-bit pwm timer #5 8-bit pwm timer #6 2-channel 8-bit pwm timer 8-bit timer #1 8-bit timer #2 8-bit serial buzzer output n-ch open-drain i/o port 8-bit up/down counter
21 mb89670/a series n cpu core 1. memory space the microcontrollers of the mb89670/a series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89670/a series is structured as illustrated below. rom ffff h 0080 h 0000 h i/o mb89673 e000 h 0100 h mb89p677a mb89677a mb89pv670a programmable rom ffff h 0080 h 0000 h i/o 0100 h ffff h 0080 h 0000 h i/o external area 0100 h 0200 h 0480 h 4000 h ram register ram register ram 0200 h 0200 h 0480 h external area external area 8007 h 8000 h option prom (one-time prom product)* * 8007 h 8000 h 8000 h 8007 h * register programmable rom *: since addresses 8000 h to 8006 h for the mb89p677a comprise an option area, do not use this area for the other products in this series. memory space
22 mb89670/a series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
23 mb89670/a series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
24 mb89670/a series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89677a. on the mb89673, there are 16 banks in internal ram. the remaining 16 banks can be extended externally by allocating an external ram to addresses 0180 h to 01ff h using an external circuit. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
25 mb89670/a series n i/o map C: unused, x: undefined, m: set using the mask option (continued) address read/write register name register description initial value 00 h (r/w) pdr0 port 0 data register x x x x x x x x b 01 h (w) ddr0 port 0 data direction register 0 0 0 0 0 0 0 0 b 02 h (r/w) pdr1 port 1 data register x x x x x x x x b 03 h (w) ddr1 port 1 data direction register 0 0 0 0 0 0 0 0 b 04 h (r/w) pdr2 port 2 data register 0 0 0 0 0 0 0 0 b 05 h (w) bctr external bus pin control register x x x x x x 0 1 b 06 h vacancy 07 h (r/w) sycc system clock control register x C C m mx 0 0 b 08 h (r/w) stbc standby control register 0 0 0 1 x x x x b 09 h (r/w) wdte watchdog timer control register x x x x x x x x b 0a h (r/w) tbcr time-base timer control register 0 0 x x x 0 0 0 b 0b h vacancy 0c h (r/w) pdr3 port 3 data register x x x x x x x x b 0d h (w) ddr3 port 3 data direction register 0 0 0 0 0 0 0 0 b 0e h (r/w) pdr4 port 4 data register x x x x x x x x b 0f h (w) ddr4 port 4 data direction register 0 0 0 0 0 0 0 0 b 10 h (r/w) pdr5 port 5 data register 1 1 1 1 1 1 1 1 b 11 h (r) pdr6 port 6 data register x x x x x x x x b 12 h (r/w) ppcr port 6 pull-up control register 0 0 0 0 0 0 0 0 b 13 h (r/w) pdr7 port 7 data register x 1 1 1 1 1 1 1 b 14 h (r/w) pdr8 port 8 data/port 7 swiching register 0 0 1 1 1 1 1 1 b 15 h (r/w) buzr buzzer control register x x x x x 0 0 0 b 16 h (r/w) cntr pwm control register #3 0 0 0 0 0 0 0 0 b 17 h (r/w) comp pwm compare register #3 x x x x x x x x b 18 h (r/w) tmcr 16-bit timer control register 0 0 0 0 0 0 0 0 b 19 h (r/w) tchr 16-bit timer count register h 0 0 0 0 0 0 0 0 b 1a h (r/w) tclr 16-bit timer count register l 0 0 0 0 0 0 0 0 b 1b h vacancy 1c h (r/w) smr serial mode register 0 0 0 0 0 0 0 0 b 1d h (r/w) sdr serial data register x x x x x x x x b 1e h vacancy 1f h vacancy
26 mb89670/a series C: unused, x: undefined, m: set using the mask option (continued) address read/write register name register description initial value 20 h (r/w) adc1 a/d converter control register 1 0 0 0 0 0 0 0 0 b 21 h (r/w) adc2 a/d converter control register 2 x 0 0 0 0 0 0 1 b 22 h (r/w) adch a/d converter data register h C C C C C C x x b 23 h (r/w) adcl a/d converter data register l x x x x x x x x b 24 h (r/w) t2cr timer 2 control register x 0 0 0 x x x 0 b 25 h (r/w) t1cr timer 1 control register x 0 0 0 x x x 0 b 26 h (r/w) t2dr timer 2 data register x x x x x x x x b 27 h (r/w) t1dr timer 1 data register x x x x x x x x b 28 h (r/w) cntr1 pwm timer control register 1 0 0 0 0 0 0 0 0 b 29 h (r/w) cntr2 pwm timer control register 2 0 0 0 0 0 0 0 0 b 2a h (r/w) cntr3 pwm timer control register 3 x x x 0 0 0 0 0 b 2b h (w) comr2 pwm timer compare register 2 x x x x x x x x b 2c h (w) comr1 pwm timer compare register 1 x x x x x x x x b 2d h vacancy 2e h vacancy 2f h vacancy 30 h (r) (w) udcr1 rcr1 up/down counter register 1 reload compare register1 xxxx xxxxb xxxx xxxxb 31 h (r) (w) udcr2 rcr2 up/down counter register 2 reload compare register2 xxxx xxxxb xxxx xxxxb 32 h (r/w) ccra1 counter control register a1 0 0 0 0 0 0 0 0 b 33 h (r/w) ccra2 counter control register a2 0 0 0 0 0 0 0 0 b 34 h (r/w) ccrb1 counter control register b1 0 0 0 0 0 0 0 0 b 35 h (r/w) ccrb2 counter control register b2 0 0 0 0 0 0 0 0 b 36 h (r/w) csr1 counter status register 1 0 0 0 0 0 0 0 0 b 37 h (r/w) csr2 counter status register 2 0 0 0 0 0 0 0 0 b 38 h (r/w) eic1 external interrupt 1 control register 1 0 0 0 0 0 0 0 0 b 39 h (r/w) eic2 external interrupt 1 control register 2 0 0 0 0 0 0 0 0 b 3a h (r/w) eie2 external interrupt 2 enable register 0 0 0 0 0 0 0 0 b 3b h (r/w) eif2 external interrupt 2 flag register x x x x 0 0 0 0 b 3c h vacancy 3d h vacancy 3e h vacancy 3f h vacancy
27 mb89670/a series (continued) C: unused, x: undefined, m: set using the mask option * : for the mb89673, these are vacancies. note: do not use vacancies. address read/write register name register description initial value 40 h (r/w) usmr uart mode register 0 0 0 0 0 0 0 0 b 41 h (r/w) uscr uart control register 0 0 0 0 0 0 0 0 b 42 h (r/w) ustr uart status register 0 0 0 0 1 x x x b 43 h (r) (w) rxdr txdr uart receiver data register uart transmitter data register xxxx xxxxb xxxx xxxxb 44 h vacancy 45 h (r/w) rrdr baud rate generator reload data register x x x x x x x x b 46 h vacancy 47 h vacancy 48 h * (r/w) cntr #4 pwm timer control register #4 0 x 0 0 0 0 0 0 b 49 h * (r/w) comp #4 pwm timer compare register #4 x x x x x x x x b 4a h * (r/w) cntr #5 pwm timer control register #5 0 x 0 0 0 0 0 0 b 4b h * (r/w) comp #5 pwm timer compare register #5 x x x x x x x x b 4c h * (r/w) cntr #6 pwm timer control register #6 0 x 0 0 0 0 0 0 b 4d h * (r/w) comp #6 pwm timer compare register #6 x x x x x x x x b 4e to 7a h vacancy 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 1 1 1 1 1 1 1 1 b 7d h (w) ilr2 interrupt level setting register 2 1 1 1 1 1 1 1 1 b 7e h (w) ilr3 interrupt level setting register 3 1 1 1 1 1 1 1 1 b 7f h vacancy
28 mb89670/a series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set at the same voltage. take care so that avr does not exceed av cc + 0.3 v and av cc does not exceed v cc , such as when power is turned on. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v * av cc v ss C 0.3 v cc + 0.3 v a/d converter reference input voltage avr v ss C 0.3 v cc + 0.3 v avr must not exceed av cc + 0.3 v. input voltage v i v ss C 0.3 v cc + 0.3 v output voltage v o1 v ss C 0.3 v cc + 0.3 v except p80 to p85 v o2 v ss C 0.3 v ss + 7.0 v p80 to p85 l level maximum output current i ol 20ma l level average output current i olav1 4ma average value (operating current operating rate) i olav2 8ma average value (operating current operating rate) p80 to p85 l level total maximum output current ? i ol 100ma l level total average output current ? i olav 40ma average value (operating current operating rate) h level maximum output current i oh C20ma h level average output current i ohav C4ma average value (operating current operating rate) h level total maximum output current ? i oh C50ma h level total average output current ? i ohav C20ma average value (operating current operating rate) power consumption p d 300mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
29 mb89670/a series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. figure 1 operating voltage vs. clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an minimum execution time of 4/f c . since the operating voltage range is dependent on the minimum execution time, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max. power supply voltage v cc 2.2* 6.0 v normal operation assurance range mb89673/677a 2.7* 6.0 v normal operation assurance range mb89pv670a/p677a 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v operating temperature t a C40 +85 c 1 2 3 4 5 6 1.0 10.0 operation assurance range 5.0 clock operating frequency (mhz) note: the shaded area is assured only for the mb89673/677a. 2.0 3.0 4.0 6.0 7.0 8.0 9.0 a/d converter accuracy assured in the v cc = av cc = 3.5 v to 6.0 v range. 4.0 0.4 0.8 2.0 minimum execution time ( m s) operating voltage (v)
30 mb89670/a series 3. dc characteristics (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p30 to p37, p40 to p47 0.7 v cc ? v cc + 0.3 v p32 to p37, p44, and p47 are port input. v ihs rst , mod0, mod1, p32 to p37, p44, p47, p60 to p67, p70 to p76 0.8 v cc ? v cc + 0.3 v p32 to p37, p44, and p47 are peripheral input. l level input voltage v il p00 to p07, p10 to p17, p30 to p37, p40 to p47 v ss - 0.3 ? 0.3 v cc v p32 to p37, p44, and p47 are port input. v ils rst , mod0, mod1, p32 to p37, p44, p47, p60 to p67, p70 to p76 v ss - 0.3 ? 0.2 v cc v p32 to p37, p44, and p47 are peripheral input. open-drain output pin application voltage v d p80 to p85 v ss - 0.3 ? v ss + 6.0 v h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p71, p72, p74, p75 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p76 i ol = 4.0 ma ?? 0.4 v v ol2 p80 to p85 i ol = 10 ma ?? 0.5 v v ol3 rst i ol = 4.0 ma 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p76, mod0, mod1 0.0 v < v i < v cc 5 m a without pull- up resistor i li2 p80 to p85 0.0 v < v i < v cc 1 m a pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p60 to p67, p70 to p76, rst v i = 0.0 v 25 50 100 k w with pull-up resistor
31 mb89670/a series (continued) (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: the measurement conditions of the power supply current are as follows: the external clock and open output pins. *2: for information on t inst , see (4) instruction cycle in 4. ac characteristics. parameter symbol pin condition value unit remarks min. typ. max. power supply current *1 i cc1 v cc f c = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 1220ma i cc2 f c = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 1 2ma mb89673 mb89677a mb89pv670a 1.52.5ma mb89p677a i ccs1 f c = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 3 7ma i ccs2 f c = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 11.5ma i cch v cc = 3.0 v t a = +25 c stop mode 1ma i a av cc f c = 10 mhz when a/d converter starts 6 8ma i ah f c = 10 mhz t a = +25 c when a/d converter stops 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf sleep mode
32 mb89670/a series 4. ac characteristics (1) reset timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
33 mb89670/a series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle parameter symbol pin condition value unit remarks min. max. clock frequency f c x0, x1 110mhz clock cycle time t xcyl x0, x1 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf x0 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c , 8/f c , 16/f c , 64/f c m s (4/f c ) t inst = 0.4 m s when operating at f c = 10 mhz 0.2 v cc 0.8 v cc x0 0.2 v cc 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open f c c1 c2 t xcyl p wh p wl t cr t cf x0 and x1 timing and conditions clock conditions
34 mb89670/a series (5) recommended resonator manufacturers inquiry: fujitsu limited far part number (built-in capacitor type) frequency initial deviation of far frequency (t a = +25 c) temperature characteristics of far frequency (t a = C20 c to +60 c) far-c4cb-08000-m02 8.00 mhz 0.5% 0.5% far-c4cb-10000-m02 10.00 mhz 0.5% 0.5% sample application of piezoelectric resonator (far series) x0 x1 far* c1 c2 *: fujitsu acoustic resonator c1 = c2 = 20 pf? pf (built-in far)
35 mb89670/a series inquiry: kyocera corporation avx corporation north american sales headquarters: tel 1-803-448-9411 avx limited european sales headquarters: tel 44-1252-770000 avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. murata electronics north america, inc.: tel 1-404-436-1300 murata europe management gmbh: tel 49-911-66870 murata electronics singapore (pte.) ltd.: tel 65-758-4233 resonator manufacturer* resonator frequency c1 (pf) c2 (pf) r (k w ) kyocera corporation kbr-7.68mws 7.68 mhz 33 33 kbr-8.0mws 8.0 mhz 33 33 murata mfg. co., ltd. csa8.00mtz 8.0 mhz 30 30 sample application of ceramic resonator x0 x1 c1 c2 *
36 mb89670/a series (6) clock output timing (av cc = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. cycle time t cyc clk 1/2 t inst * m s clk - ? clk t chcl clk 1/4 t inst C 0.07 1/4 t inst m s 2.4 v clk 0.8 v t cyc 2.4 v t chcl
37 mb89670/a series (7) bus read timing (av cc = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. valid address ? rd time t avrl rd , a15 to 08, ad7 to 0 1/4 t inst * C 0.06 m s rd pulse width t rlrh rd 1/2 t inst *C 0.02 m s valid address ? data read time t avdv ad7 to 0, a15 to 08 1/2 t inst * m swait rd ? data read time t rldv rd , ad7 to 0 1/2 t inst *C 0.08 m sno wait rd - ? data hold time t rhdx ad7 to 0, rd 0ns rd - ? ale - time t rhlh rd , ale 1/4 t inst * C 0.04 m s rd - ? address loss time t rhax rd , a15 to 08 1/4 t inst * C 0.04 m s rd ? clk - time t rlch rd , clk 1/4 t inst * C 0.04 m s clk ? rd - time t clrh rd , clk 0 ns rd ? bufc time t rlbl rd , bufc C5 ns bufc - ? valid address time t bhav a15 to 08, ad7 to 0, bufc 5ns ale ad a rd bufc clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v t rhdx t bhav t rlbl t clrh t rhlh t avdv t rlch t rhax t rldv t avrl t rlrh
38 mb89670/a series (8) bus write timing (av cc = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: these characteristics are also applicable to the bus read timing. *2: for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. valid address ? ale time t avll ad7 to 0, ale, a15 to 08 1/4 t inst * 2 C 0.064 m s ale time ? address loss time t llax ad7 to 0, ale, a15 to 08 5 *1 ns valid address ? wr time t avwl wr , ale 1/4 t inst * 2 C 0.06 m s wr pulse width t wlwh wr 1/2 t inst * 2 C 0.02 m s writing data ? wr - time t dvwl ad7 to 0, wr 1/2 t inst * 2 C 0.06 ns wr - ? address loss time t whax wr , a15 to 08 1/4 t inst * 2 C 0.04 m s wr - ? data hold time t whdx ad7 to 0, wr 1/4 t inst * 2 C 0.04 m s wr - ? ale - time t whlh wr , ale 1/4 t inst * C 0.04 m s wr ? clk - time t wlch wr , clk 1/4 t inst * 2 C 0.04 m s clk ? wr - time t clwh wr , clk 0 ns ale pulse width t lhll ale 1/4 t inst * 2 C 0.035 m s ale ? clk - time t llch ale, clk 1/4 t inst * 2 C 0.03 m s ale ad a wr clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t clwh 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t llax t wlwh t dvwh t lhll t llch t whlh t avll t whdx t wlch t whax t avwl
39 mb89670/a series (9) ready input timing (av cc = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : these characteristics are also applicable to the read cycle. parameter symbol pin condition value unit remarks min. max. rdy valid ? clk - time t yvch rdy, clk 60 ns * clk - ? rdy invalid time t chyx rdy, clk 0 ns * clk ale ad a wr rdy address t yvch t chyx t yvch t chyx 2.4 v 2.4 v note: the bus cycle is also extended in the read cycle in the same manner. data
40 mb89670/a series (10) serial i/o timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s 0.8 v 2.4 v t scyc 2.4 v t slov 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si internal shift clock mode t slsh 2.4 v t slov t shix 0.8 v cc 0.8 v t ivsh 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t shsl 0.8 v cc 0.2 v cc 0.2 v cc sck so si external shift clock mode
41 mb89670/a series (11) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 tci 1 t inst * m s peripheral input l pulse width 1 t ihil1 tci 1 t inst * m s peripheral input h pulse width 2 t ilih2 ec, int0 to int7 2 t inst * m s peripheral input l pulse width 2 t ihil2 ec, int0 to int7 2 t inst * m s peripheral input h pulse width 3 t ilih3 adst a/d mode 64 t inst * m s peripheral input l pulse width 3 t ihil3 adst 64 t inst * m s peripheral input h pulse width 3 t ilih3 adst sense mode 64 t inst * m s peripheral input l pulse width 3 t ihil3 adst 64 t inst * m s 0.2 v cc 0.8 v cc t ihil2 0.8 v cc ec int0 to int7 0.2 v cc t ilih2 0.2 v cc 0.8 v cc t ihil3 0.8 v cc adst 0.2 v cc t ilih3 0.2 v cc 0.8 v cc t ihil1 0.8 v cc tci 0.2 v cc t ilih1
42 mb89670/a series (12) up/down counter input timing (av cc = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. ain input 1 pulse width t ahl p36, p37, p33, p34 2 t inst * m s ain input 0 pulse width t all 2 t inst * m s bin input 1 pulse width t bhl 2 t inst * m s bin input 0 pulse width t bll 2 t inst * m s ain - ? bin - time t aubu 1 t inst * m s bin - ? ain time t buad 1 t inst * m s ain ? bin time t adbd 1 t inst * m s bin ? ain - time t bdau 1 t inst * m s bin - ? ain - time t buau 1 t inst * m s ain - ? bin time t aubd 1 t inst * m s bin ? ain time t bdad 1 t inst * m s ain ? bin - time t adbu 1 t inst * m s zin input 1 pulse width t zhl p32, p35 1 t inst * m s zin input 0 pulse width t zll 1 t inst * m s
43 mb89670/a series bin t ahl ain t all t aubu t buad t adbd t bdau t bhl t bll ain t bhl bin t bll t buau t aubd t bdad t adbu t ahl t all zin t zhl t zll 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc
44 mb89670/a series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, f c = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) precautions: ? the smaller | avr C av ss |, the greater the error would become relatively. ? the output impedance of the external circuit for the analog input must satisfy the following conditions: output impedance of the external circuit < approx. 10 k w if the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 m s at 10 mhz oscillation). an analog input equivalent circuit is shown below. since the a/d converter contains sample hold circuit, the level of the analog input pin might not stabilize within the sampling period after a/d activation, resulting in inaccurate a/d conversion values, if the input impedance to the analog pin is too high. be sure to maintain an appropriate input impedance to the analog pin. it is recommended to keep the input impedance to the analog pin not exceed 10 k w . if it exceeds 10 k w , it is recommended to connect a capacitor of approx. 0.1 m f for the analog input pin. except for the sampling period after a/d activation, the input leakage current of the analog input pin is less than 10 m a. parameter symbol pin value unit remarks min. typ. max. resolution 10 bit linearity error 2.0 lsb av cc = avr = v cc differential linearity error 1.5 lsb total error 3.0 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to an7 avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 4lsb a/d mode conversion time 13.2 m s at 10-mhz oscillation analog port input current i ain an0 to an7 10 m a analog input voltage an0 to an7 0 avr v reference voltage avr 0 av cc v reference voltage supply current i r avr 200 ?m a avr = 5.0 v comparator c = 60 pf r = 3 k w ( ) sample hold circuit close for approx. 15 instruction cycles after activating a/d conversion. analog channel selector r 10 k w is recommended. an if r > 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. microcontrollers internal circuit . . . .
45 mb89670/a series (1) a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter. ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error the difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. (continued) 3ff 3fe 3fd 004 003 002 001 v ot 0.5 lsb av ss 1 lsb 1.5 lsb v fst avr 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + 0.5 lsb} 1 lsb = v fst ?v ot 1022 (v) v nt ?{1 lsb n + 0.5 lsb} 1 lsb theoreticall i/o characteristics digital output analog input digital output total error actual conversion value actual conversion value theoretical value analog input total error of digital output n
46 mb89670/a series (continued) 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + v ot } v nt ?{1 lsb n + v ot } 1 lsb 004 003 002 001 av ss 3ff 3fe 3fd 3fc avr av ss avr v nt v (n+1)t ?v nt 1 lsb ?1 zero transition error digital output analog input actual conversion value theoretical value actual conversion value v ot (actual measured value) full-scale transition error digital output analog input actual conversion value actual conversion value v fst (actual measured value) theoretical value differential linearity error digital output analog input v (n + 1)t actual conversion value actual conversion value theoretical value n + 1 n n 1 n 2 linearity error digital output analog input v ot (actual measured value) v fst (actual measured value) actual conversion value theoretical value actual conversion value linearity error of digital output n = differential linearity error of digital output n =
47 mb89670/a series n example characteristics 012 3 456 7 5.0 v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils v cc (v) v in (v) t a = +25 c 0.0 1.0 v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 v cc ? oh (v) t a = +25 c v cc ? oh vs. i oh (1) l level output voltage (2) h level output voltage (3) h level input voltage/l level input (4) h level input voltage/l level input voltage (cmos input) voltage (hysteresis input) v ihs : threshold when input voltage in hysteresis v ils : threshold when input voltage in hysteresis characteristics is set to h level characteristics is set to l level 010 123456789 0.1 0.2 0.3 0.4 0.5 v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v v ol (v) 0.0 i ol (ma) t a = +25 c v ol vs. i ol 012 3 456 7 5.0 v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v cc (v) v in (v) t a = +25 c
48 mb89670/a series (5) power supply current (external clock) (6) pull-up resistance 25 20 15 10 5 i cc (ma) 3456 i cc1 vs. v cc , i cc2 vs. v cc t a = +25 c f c = 10 mhz external clock i cc1 (divide by 4) i cc2 (divide by 64) 7 2 0 v cc (v) 25 20 15 10 5 i ccs (ma) 3456 t a = +25 c f c = 10 mhz external clock i ccs1 vs. v cc , i ccs2 vs. v cc 7 i ccs1 (divide by 4) i ccs2 (divide by 64) 2 0 v cc (v) v cc (v) 234 5 6 10 1 100 1000 r pull (k w ) r pull vs. v cc 50 500 t a = +25 c
49 mb89670/a series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
50 mb89670/a series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
51 mb89670/a series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
52 mb89670/a series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
53 mb89670/a series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
54 mb89670/a series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
55 mb89670/a series n mask options n ordering information no. part number mb89673 mb89677a mb89p677a mb89pv670a specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p10 to p17, p30 to p37, p40 to p47, p70 to p76 selectable by pin selectable by pin fixed to without pull-up resistor 2 pull-up resistors p00 to p03 selectable by pin selectable in 4-pin unit 3 pull-up resistors p04 to p07 selectable by pin selectable in 4-pin unit 4 power-on reset with power-on reset without power-on reset selectable selectable fixed to with power-on reset 5 oscillation stabilization time selection (at 10 mhz) approx. 2 18 /f c (about 26.2 ms) approx. 2 17 /f c (about 13.1 ms) approx. 2 14 /f c (about 1.6 ms) approx. 2 4 /f c (about 0 ms) f c : clock frequency selectable selectable fixed to approx. 2 18 /f c (approx. 26.2 ms) 6 reset pin output with reset output without reset output selectable selectable fixed to with reset output part number package remarks mb89673pf mb89677apf mb89p677apf 80-pin plastic qfp (fpt-80p-m06) mb89673pfm mb89677apfm mb89p677apfm 80-pin plastic qfp (fpt-80p-m11) MB89P670ACF 80-pin ceramic mqfp (mqp-80c-p01)
56 mb89670/a series n package dimensions C.001 +.002 C0.02 +0.05 +0.20 C0.10 +.008 C.004 lead no. 60 41 61 80 1 40 21 20 nom (.591) ref (.486) 15.00 12.35 .005 0.127 (.012.004) 0.300.10 0.65(.0256)typ 14.000.10(.551.004)sq 16.000.20(.630.008)sq (stand off) (.020.008) (.004.004) 0.100.10 0.500.20 0 10 details of "a" part "a" 1.50 .059 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f80016s-1c-2 c dimensions in mm (inches) 80-pin plastic qfp (fpt-80p-m11)
57 mb89670/a series "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 c 80-pin plastic qfp (fpt-80p-m06) dimensions in mm (inches)
58 mb89670/a series +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 index typ 4.50(.177) typ 6.00(.236) index area 1.50(.059)typ 1.00(.040)typ typ 1.00(.040) typ 1.50(.059) (.0315.010) 0.800.25 1.20 .047 12.00(.472)typ (.0315.010) 0.800.25 ref 18.40(.724) (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 8.70(.343) (.006.002) 0.150.05 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m80001sc-4-2 c 80-pin ceramic mqfp dimensions in mm (inches) (mqp-80c-p01)
59 mb89670/a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 1015, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited no. 51 bras basah road, plaza by the park, #06-04 to #06-07 singapore 189554 tel: 336-1600 fax: 336-1609 f9602 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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